module led
	(
		input wire CLK_IN,
		output wire LED1
	);

	reg [26:0] count;
	
	initial
	begin
		count=27'b0;
	end

	always @(posedge CLK_IN)begin
		count <= count + 1'b1;
	end
	
	assign LED1 = count[25];
endmodule
